Cache memories in dataflow architecture

The recent advance in dataflow processing - to combine the dataflow paradigm with the control flow paradigm - has brought out many new challenging issues. This hybrid organization has made it possible to study familiar control flow concepts within the framework of the dataflow architecture. The concept of cache memory has proven its effectiveness in the von Neumann architecture due to the spatial and temporal localities which govern the organization of the conventional programming environment. A dataflow paradigm, does not imply to the locality. However, dataflow programs can be reordered to enhance the locality of instruction references. This can be achieved by careful partitioning of a dataflow program into vertical layers of data dependent instructions, and proper distribution and allocation of the recurrence portions of the dataflow program. Enhancing the locality of data references in flow architecture is a more challenging problem. This paper studies the design of instruction, data (operand) and I-Structure cache memories. The performance results obtained using various benchmark programs are presented and analyzed.