The Heterogeneous Architecture of Multi-Core Research and Design

Aiming at the problem that it was difficult to improve the processor performance only by improve the frequency of the clock, as well as superscalar pipeline stall, the paper introduced an architecture of heterogeneous Multi-Core processor which used the Loop Detector, special Queuing Backup Ins Queue, C-Core processor controller, and C-Bus which among of E-Core. The architecture not only optimized loop program, and avoided the pipeline flushed due to branch miss-predict. So the architecture could improve overall efficiency of Multi-Core processor.