Evaluation of interconnection capacitances in IC's with heterogeneous isolating materials

Parameters of interconnection lines have an effect on the electrical parameters of modern VLSI chips, so precise models of interconnection capacitances are indispensable in verification of the design. In our previous works we have shown importance of geometric configuration of the interconnection bus, taking into account further neighbourhood, and proposed a model of corresponding capacitances, verified numerically and experimentally. Our model was developed for technologies using only SiO
₂
as the isolation material between interconnection lines and metal layers. In most advanced technologies low-k materials displace SiO
₂
, as they enable to reduce capacitances significantly. In this paper we present results of our studies on usability of our model in the cases of technologies using different and heterogeneous isolating materials in respect of dielectric permittivity.