Synchronization on heterogeneous multiprocessor systems

To meet the exponential increase in processing requirements of present day embedded system applications, system-on-chip (SoC) designs increasingly have multiple processing elements on the same die. The functionality of these processing elements varies considerably, and includes hardware accelerators for specific digital signal processing (DSP) kernels, high-performance DSP cores, and low-power application processors. While executing applications, these processing elements typically share system memory and peripherals, and hence need synchronization to maintain system integrity. Further complicating the issue is the fact that these processing elements can be custom designed or off-the-shelf intellectual property (IP) cores that are generally not designed for operation in multiprocessor environments, and consequently lack multiprocessor synchronization support. Hence there is a need for simple and elegant low-power, low-latency techniques for synchronization support that can be seamlessly integrated and require little or no modifications to the already pre-verified processing elements. In this paper, we describe synchronization counters, a mechanism that allows seamless implementation of low-latency multiprocessor synchronization with incremental hardware penalty. This mechanism is usable in heterogeneous multiprocessor environments even when the individual processing elements lack native synchronization support. The synchronization counters are implemented and verified on a four-processor SoC targeted for handheld devices, the Sandbridge Technologies SB3500. The SoC contains three special purpose DSPs and an ARM application processor, sharing system memory and peripherals.