Reducing Leakage Power of JPEG Image on Asymmetric SRAM

Leakage power becomes a key challenge and occupies an increasing portion of the total power consumption in nano-scale circuit design. There are many novel cache designs to reduce the leakage power based on the characteristics of programs. One of them is Asymmetric SRAM that can reduce leakage power on cache while storing bit "0". In this paper, we propose two algorithms, value-position-switch algorithm and code-bit-switch algorithm, to make the JPEG image bias on bit "0" based on Asymmetric SRAM. The value-position-switch algorithm and codebit-switch algorithm can reduce the amount of bit "1" in Huffman coded data up to 7.33% and 25.20%, respectively. The overheads of instruction count, cycle count and power consumption for these two algorithms are negligible (< 0.3%). To the best of our knowledge, this paper is the first study to reduce leakage power in application-level by utilizing the feature of Asymmetric SRAM.