A 9.43-ENOB 160MS/s 1.2V 65nm CMOS ADC based on multi-stage amplifiers

A 12-bit 1.2V 160MS/s pipeline ADC for high-definition video systems is presented. The proposed multipath frequency-compensation technique enables the conventional RNMC-based three-stage amplifier to achieve a stable operation at a sampling rate of 160MS/s. The measured differential and integral nonlinearities of the prototype ADC implemented in a 65nm CMOS process are less than 0.69LSB and 1.00LSB respectively. The ADC shows a maximum SNDR of 58.5dB and 53.1dB and a maximum SFDR of 76.0dB and 67.8dB at 160MS/s and 200MS/s, respectively. The ADC with an active die area of 0.72mm
²
shows a FoM of 0.75pJ/conv-step at 160MS/s and 1.2V.