A simulation-based protocol-driven scan test design rule checker

The test protocol for a serial scan design comprises the serial scan-in, parallel measure & capture, and serial scan-our operations. Through symbolic simulation of the protocol, compliance with scan design rules can be verified. For example, simulation of the scan-in operation should establish an arbitrary known state in all sequential cells within the design. A cell whose state is not controllable represents a design rule violation. This approach is both more flexible and more robust than previous work, and addresses current issues with the integration of internal scan and boundary scan. Further, the approach links the tasks of design rule checking and the formatting of the output of Automatic Test Pattern Generation (ATPG) into a scan test program. This approach has been applied successfully to a wide variety of designs, up to 700 K gates.