Design of a digital fuzzifier based on successive approximation

In this paper, we present a design of a digital dynamic fuzzifier based on successive approximation. It is suitable for on-line training or on-line adaptive fuzzy control systems. With the parameters of the triangle or trapezoid membership functions and the number to be fuzzified as the inputs, it automatically calculated the proper membership values for the fuzzy control systems. The chip is designed with a standard cell approach and implemented in the MOSIS CMOS 2 /spl mu/m technology. For 4-bit inputs, there are 1,744 transistors in the chip and the size of the chip is 1,515 /spl mu/m by 1,088 /spl mu/m. From the hspice simulation results with 4-bit numbers as inputs, the maximum delay is 30 ns for a two-bit output.