Modelling the single-electron transistor with piecewise linear functions

Hybrid systems built up with CMOS devices and Single-Electron Transistors (SET), have been foreseen as a potential alternative in the long term when CMOS downscaling reaches its physical fundamental limits. Although there are still many problems in the fabrication of these nanoelectronic devices, the design flow for hybrid systems requires further development not only in those aspects directly linked to the design and synthesis, but also in aspects regarding the verification of the design, such as electrical simulation. This paper introduces an appropriate model for the SET that can be easily implemented for co-simulation of hybrid systems. The model constitutes a functional model for the SET in the form of an explicit piecewise linear (PWL) formulation that can be easily coded into a high level language.