Impact of substrate coupling induced by 3D-IC architecture on advanced CMOS technology

A TCAD-based simulation approach is proposed to study the impact of transient coupling that occurs within a generic 3D integration on 65 nm technology based CMOS devices. This coupling is mainly due to signals applied on redistribution layer (RDL) and through-silicon vias (TSV). These both 3D-inherent metal structures may cause variations on normal operating conditions of advanced devices. Influence of design and technology parameters such as keep-away zone, TSV/RDL isolation oxide thicknesses and remaining silicon thickness are investigated on NMOS transistors, in order to extract application-driven 3D-specific design rules. We also show that significant variations on saturation drain current and especially on leakage current appear each time TSV/RDL-applied signals switch. These current variations are strongly dependent on rise and fall potential ramp times applied on TSV or RDL. Shorter rise or fall ramp time induces a more aggressive coupling on devices. In certain cases, it may be destructive for advanced CMOS technology. Dynamic variations on saturation drain current can be tolerated under specific design rules and process options but those on leakage current are very important compared to static leakage current value, and are of the order of 10
^-6
A/mum.