Design of Totally Self-Checking Sequential Circuits

Methods of designing of totally self checking sequential machines are presented in this paper. The main problem in TSC sequential machines (TSC SM) designing is synthesis TSC functional excitation circuit. Formal condition of self testing (ST) property for AND-OR structures are given. New method of circuit minimization is presented and ST of minimized circuits is proofed. We also present a methodology of designing of TSC SM. Owing to our methods we can design TSC circuits in a fully automatic way.