Novel technique to reduce latch-up risk due to ESD protection devices in Smart Power technologies

N-well pockets connected to the cathode of ESD diodes may be source of parasitic electrons current in P
^-
/P
⁺⁺
substrates. In this paper a methodology to reduce this latch-up risk is proposed. The electrical performances of this protection technique have been characterized and the results have been validated by device simulations.