An active ESD protection technique for the power domain boundary in a deep submicron IC

A novel ESD protection technique which prevents failure of boundary circuits in an IC with separated power pins from ESD stresses is proposed. In the proposed technique, the boundary circuits which are composed of drivers or receivers are controlled by an ESD detector to reduce stresses on the circuits during ESD events. Measurement results and physical analysis show that this technique improves the equivalent HBM level from 1.9 kV to 2.7 kV in test chips fabricated in a 90 nm CMOS process.