A High-Speed Low-Noise CMOS Image Sensor With 13-b Column-Parallel Single-Ended Cyclic ADCs

A high-performance CMOS image sensor (CIS) with 13-b column-parallel single-ended cyclic ADCs is presented. The simplified single-ended circuits for the cyclic ADC are squeezed into a 5.6-mum-pitch single-side column. The proposed internal reference generation and return-to-zero digital signal feedback techniques enhance the ADC to have low read noise, a high resolution of 13 b, and a resulting dynamic range of 71 dB. An ultralow vertical fixed pattern noise of 0.1 e
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is attained by a digital CDS technique, which performs A/D conversion twice in a horizontal scan period (6 mus). The implemented CIS with 0.18-mum technology operates at 390 frames/s and has 7.07-V/lx middots sensitivity, 61- muV/e
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conversion gain, 4.9-e
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read noise, and less than 0.4 LSB differential nonlinearity.