A fetch-and-op implementation for parallel computers

A fetch-and-op circuit is described. A bit-serial circuit-switched implementation requires only five gates per node in a binary tree. This circuit is also capable of test-and-set primitives (priority circuits) and swap operators, as well as AND and OR operations used in SIMD (single-instruction, multiple-data-stream) tests such as branch on all carries set. It provides an alternative implementation for the combining fetch-and-add circuit to the one designed for the Ultracomputer project; this implementation is suited to SIMD computing and can be adapted to MIMD (multiple-instruction, multiple-data stream) computing.<
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