Investigation of wafer level reliability of amorphous Si antifuses for high density FPGAs

The methodology and results of the wafer level reliability assessment of the antifuse devices are presented here. Previously we established the link formation and link failure models. According to these models the link formation is due to the melting of electrodes at the highest temperature area. Also, the switch-off phenomenon has been explained as the melting of the conductive link caused by joule heating of the link. Detail mathematical treatment has been presented here and the theory shows good agreement with the experimental data. Furthermore, the WLR method of determining the lifetime of unprogrammed and programmed antifuses has been presented. The lifetime of unprogrammed and programmed antifuses has been shown to be in excess of 10 years.