One-phase technology mapping for EPGAs using extended GBDD hash tables

An efficient and novel algorithm, for technology mapping of electrically programmable gate arrays (EPGAs) is proposed. In this algorithm, the personalization of an uncommitted logic module is done by stuck-at fault and/or bridging fault assignments. This technology mapping algorithm combines decomposition and covering into one phase. In order to carry out Boolean matching fast, an extended GBDD hash table constructed by permuting and bridging inputs of a module is developed to test whether a portion of given combinational logic circuit can be implemented by personalizing a module quickly. Some experimental results on standard benchmarks are reported.