A macromodel compaction scheme for the fast simulation of large linear mesh circuits

Analysis of large linear mesh circuits is critical in modern IC extraction and verification tools due to the complex 3-D effects associated with parasitic coupling through interconnects and the chip substrate. The limited availability of computer resources, however, is a major obstacle in the fast and accurate analysis of such circuits. This paper introduces a technique that divides the mesh into a number of partitions, develops macromodels of each partition using a compaction technique and then combines them in a nested fashion to determine a macromodel for the original mesh circuit, which can then be used in simulation. This method makes much better use of CPU time and memory and allows for the fast analysis of extremely large meshes.