A survey on leakage control techniques in wide-OR domino circuits

In this paper, we compare different existing keeper techniques for reducing power consumption of wide domino logic circuits. We will compare power consumption plus area overhead of each of these methods, with the conventional keeper circuit. A 16-bit multiplexer circuit, in 0.13 mum CMOS technology operating at a frequency of 500 MHz is our test-bench. Simulations show split-domino (SD), with 53% less power consumption, and 10.5% more area, has the best performance.