Creating an affordable 22nm node using design-lithography co-optimization

Extended the required time-to-market with economically acceptable yield levels and maintaining them in volume production has become a daunting task for the advanced technology nodes. These difficulties are primarily attributable to the increase in process variability that is incurred while aggressively scaling technology nodes which are based on the same fundamental device architectures and process solutions. The introduction of a Metal Gate/High-K (MGHK) stack at the 32/28nm technology node will help in addressing the random variations due to random dopant fluctuations (RDF), but its benefit will be exhausted after a single process generation [3]. As a result, for the 22/20nm technology nodes, the only hope to limit RDF will be to adopt novel device architecture, such as FinFET anf Ultra Thin Body or Fully Depleted SOI, that would reduce the dopant concentration in the channel.