Register Multimapping: A technique for reducing register bank conflicts in processors with large register files

In this paper, we investigate register multimapping as a technique to reduce register bank conflicts for processors with large register files, but relatively slow clock speeds. Register multimapping involves mapping an architectural register to multiple physical registers belonging to different banks. Reads can proceed using any of the physical registers, thereby minimizing read bank conflicts. Write conflicts can be minimized by allowing delayed allocation of physical registers. Our experiments show that register multi-mapping can result in performance improvements up to 15% (10% on average) over baseline processors that are port constrained. Improvements are up to 13% (5.5% on average) over port constrained processors that support delayed allocation of registers.