Performance evaluation of on-chip register and cache organizations

Several different local memory organizations applicable for single-chip processors are compared. Several cache types-instruction, data, split, unified, stack, and top-of-stack-are considered. These are compared to multiple-register-set architectures to which various caches can also be added. The performance metric of interest is effective access time, since a wide variety of register and cache organizations are used. A model for access time and a model for chip area required for each organization form the basis for comparison. Extensive simulations of several register-memory organizations are presented. Address traces from a VAX-11/780 running systems programs were used in the simulation. The data indicate that for small area (<200 bytes), top-of-stack or instruction cache are the best choice; for intermediate area (200 to 600 bytes), a combination of top-of-stack and instruction cache is best; and for large area (>600 bytes), split or unified instruction and data caches are best. Context switch effects were measured and found to be negligible for small- and medium-size caches.<
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