CMOS Nanostructures with Improved Temperature Behavior Using Double Differential Structures

An original superior-order curvature-corrected integrated nanostructure will be presented. In order to improve the temperature behavior of the circuit, a double differential structure will be used, implementing linear and superior-order curvature corrections. The superior-order curvature-correction is achieved by taking the difference between two gate-source voltages of subthreshold-operated MOS transistors, biased at drain currents having different temperature dependencies: PTAT (Proportional To Absolute Temperature) and PTAT
²
. The SPICE simulations confirm the theoretical estimated results, showing a temperature coefficient under 11 ppm/K for an extended input range 223 K < T < 423 K and for a supply voltage of 1.8 V and a current consumption of about 1 muA results.