A 1.3GHz 350mW hybrid direct digital frequency synhesizer in 90 nm CMOS

This paper presents a low power hybrid direct digital frequency synthesizer (DDFS) with a maximum operating frequency of 1.3GHz fabricated in 90nm CMOS. The proposed hybrid design extends the resolution of the nonlinear DAC by adding a linear slope component to the sine approximation via an additional linear DAC. With an 11-bit combined DAC, this DDFS produces a minimum SFDR of 52dBc up to Nyquist at 1.3GHz while dissipating only 350mW and occupying 2mm
²
including pads. The FOM of this chip is measured at 1207.9GHz2
^ENOB
/W.