A 6-bit 50-MS/s threshold configuring SAR ADC in 90-nm digital CMOS

A threshold configuring SAR A/D converter is presented that programs its comparator threshold at runtime to approximate the input signal via binary search. Low power and small area are achieved via a fully dynamic configurable comparator and an asynchronous controller with no need for capacitor-based feedback D/A converter. A 6-bit prototype in 90-nm digital CMOS technology achieves 32-dB SNDR at 50 MS/s consuming 240 μW from 1-V analog and 0.7-V digital supplies, i.e. 150fJ/conversion-step, in a core area occupation of only 0.0055 mm
²
, a 4× improvement on state-of-the-art designs.