Sophisticated methodology of dummy pattern generation for suppressing dislocation induced contact misalignment on flash lamp annealed eSiGe wafer

Defects-induced contact misalignment when combining embedded SiGe with flash lamp annealing (FLA) on high performance 40nm CMOS process has been analyzed both by experiments and novel dislocation loop dynamics simulation. We have found that slips which are created at the SiGe dummy patterns worsen the contact misalignment for the first time. Design guide lines on shape of SiGe patterns for slip free condition have been investigated and clarified. With optimized SiGe patterns, random component of contact misalignment have been successfully reduced to lead high SRAM yields at 40nm tech node with high performance.