Vth variation and strain control of high Ge% thin SiGe channels by millisecond anneal realizing high performance pMOSFET beyond 16nm node

We have studied key parameters for controlling threshold voltage (V
_th
) variation and strain maintenance of gate first SiGe channel pMOSFETs. By overcoming 1) Ge diffusion and 2) strain relaxation during source/drain activation, we for the first time demonstrate high Ge% (50%) SiGe channel with millisecond flash anneal. Optimizing the thermal budget with millisecond anneal keeps the V
_th
variation same to Si unlike RTA anneal while still having 2.8times mobility gain. We achieved high performance SiGe pMOSFETs with appropriate V
_th
[-0.2~-0.3 V], ~1 nm EOT and superior NBTI [<30 mV] reliability for the integration of SiGe channel for pMOSFETs.