Concurrent self test of switched current circuits based on the S/sup 2/I-technique

This article presents a new concept for concurrent self test of switched current circuits based on S/sup 2/I cells as basic building blocks. Six different transistor faults were modelled and the ability to detect the various fault-situations was studied. The fault detection system presented was applied to a simple switched-current integrator in which all the different faults were introduced sequentially in all transistors. The fault coverage was derived and the result shows that a powerful system for detection of transistor faults in an analogue sampled-data system can be realised with a minimum of additional overhead circuitry.