Efficiency-Aware QoS DRAM Scheduler

For most SoCs, off-chip DRAM is an important resource that is shared by many heterogeneous function units(FU).To meet different memory access requirements by these FUs,it is crucial that the memory subsystem is capable of providing different quality of service(QoS).Due to the nature of DRAM, the available bandwidth greatly depends on the memory access sequence. However,conventional schedulers are not aware of the variable bandwidth.In this paper, a QoS scheduler is proposed by recognizing the inefficiency caused by ongoing memory accesses.The experimental results show that, the scheduler can provide bandwidth guarantee for bandwidth sensitive FUs even in the worst case scenarios. And low latency for latency sensitive FUs can be achieved when the bus is below the saturation point.