Characteristics of n-Channel MOSFETs With Tailored Source/Drain Extension for Mask ROM and EEPROM Applications

A novel 2-bits-per-transistor mask-programmable read-only memory (mask ROM) device with gate-to-drain nonoverlapped implantation (NOI) is investigated in this paper. The NOI mask ROM can be coded by using the lightly doped drain implantation mask and related processes. This simple coding scheme is fully compatible with industrial CMOS processing. The measured threshold voltage difference $\Delta V_{\rm th}$ between the two logic states (“0” and “1”) of the devices is approximately 0.6 V. Moreover, $\Delta V_{\rm th}$ can be improved when the pocket implant is incorporated into the NOI region based on the device simulation. The characteristics of this NOI mask ROM, including 2-bits-per-transistor operation, body effects, hot carrier impact, and array layouts, are investigated. By sharing the same array layout and readout circuit, the potential of NOI devices' seamless migration between the mask ROM and electrically erasable programmable read-only memory functions are also demonstrated.