The ARPA-MT Embedded SMT Processor and Its RTOS Hardware Accelerator

The high-level modeling and parameterization capabilities of current hardware description languages, as well as the huge integration capacity and flexibility provided by modern field-programmable gate arrays (FPGAs), open the way to designing processors tuned to given applications and favoring specific properties. This paper presents the Advanced Real-time Processor Architecture (ARPA)-MultiThreaded processor-a customizable, synthesizable, and time-predictable processor model optimized for multitasking real-time embedded systems, which efficiently explores modern FPGA technology. A fundamental processor component is the ARPA operating system (OS) coprocessor designed for hardware implementation of the basic real-time OS management functions, such as timing, task scheduling, synchronization and switching, efficient interrupt handling, and verification of the timing constraints. The hardware implementation of these functions allows executing them faster and more predictably, reducing the OS overhead, and improving its determinism. The performance evaluation has shown reductions of one to two orders of magnitude in the execution time of some functions of a real-time executive, in comparison with an analogous software implementation.