A 12-bit 125-MHz segmented current-steering DAC for communication application

A 12-bit 125-MHz digital-to-analog converter (DAC) for communication application is designed. It is based on current-steering segmented architecture and modified Q
²
random walk switching scheme to obtain 12-bit accuracy. A new voltage swing reduced driver (VSRD) is implemented to promote the dynamic performance. The DAC uses 0.18 µm 1.8 V standard digital CMOS technology. The die area (core) is 2.7 × 2.1mm
²
and power consumption is 37.1mA.