Split FIFO phase synchronization for high speed interconnect

This paper describes a simple method of phase synchronization for high speed communication in a large distributed network such as a parallel processor interconnect. Reducing phase delta with matched clock distribution in a distributed system is not always practical. A split FIFO phase synchronizer provides reliable data transfer at fast clock speeds and high bandwidth. A digital delay locked loop, DLL, centers the data clock midway in the data bit cell. A reset arbiter/synchronizer provides proper alignment of the read and write pointer release during initialization of the split FIFO synchronizer.