Solution and Optimization of FPGA Routing Algorithm

Optimized solvers for the Boolean Satisfiablity problem have many applications in areas such as FPGA routing, planning, and so forth. In the context of FPGA routing where routing resources are fixed, Boolean formulation methods can prove the unroutability of a given circuit, which is a clear advantage over classical net-at-a-time approaches. This paper introduces a new and efficient hybrid routing algorithm for FPGAs. Novel features of this approach include: (1) employing the Pseudo-Boolean Satisfiability to offset the disadvantage of sub-SAT formulation; (2) integrating our approach with geometric routing algorithm. Preliminary experiments results show that this approach can greatly reduce the numbers of variables and clauses, and the running time is dramatic reduced which compared with the sub-SAT.