Test generation for linear analog circuits

A test generation method for linear analog circuits is presented. The method is based on frequency domain analysis. The faults considered are abnormal value changes of elements, e.g., resistors, capacitors and inductors. The effect of design tolerance is considered in test generation. A procedure to determine the output ranges for acceptance or rejection is also proposed. The proposed method has been applied to several circuits at board level to generate test conditions for all elements to be tested. The method is also able to indicate which elements in the circuit are hard to test.