A 10 bit low-power CMOS D/A converter with on-chip gain error compensation

This paper describes a 10-bit, 500 kHz, low-power steering-current CMOS D/A converter for portable communications. A triple-segmented architecture is used to improve the linearity while minimizing the circuit area and gain error compensating circuitry is employed to correct for full-scale errors. The prototype chip fabricated in a 1.2 /spl mu/m standard CMOS technology occupies less than 0.45 mm/sup 2/ and consumes less than 2.4 mW for a 1 V output swing at 5 V supply. Full-scale voltage errors due to chip-to-chip variations are better than /spl plusmn/3% and below /spl plusmn/43 ppm//spl deg/C for temperature drifts in the range -30/spl deg/C to +85/spl deg/C.