A 14-bit 500 kHz delta-sigma ADC with 16 times oversampling

A 14-bit 500 kHz delta-sigma ADC is described that uses an oversampling ratio of only 16. A fourth-order embedded architecture is used along with a 4-bit quantizer to achieve this performance. Although previously believed to be unstable, it is shown that with proper design a robust design may be obtained. This is the lowest oversampling ratio for this resolution and bandwidth achieved to date.