Time and temperature dependence of early stage Stress-Induced-Voiding in Cu/low-k interconnects

The time and temperature dependence of Stress-Induced-Voiding below and in copper VIA's with a diameter of 80nm integrated in a k=2.5 material was studied. The focus was on the early phase of the voiding process. To accelerate the degradation, test structures with big metal plates below and/or above the VIA were used. We found two degradation mechanisms in which one dominated below and the other dominated above a certain temperature. The first mechanism has an activation energy of 0.9eV and is the result of interface-diffusion driven by a stress-gradient. This mechanism was more pronounced below the VIA, but was significant in the VIA as well. The second mechanism has an activation energy of 1.2eV, which is argued to be driven by grain boundary diffusion due to a vacancy gradient in and above the VIA. To explain both mechanisms, an addition to the traditional stress-creep model is proposed and fits our data well. Additionally, it is discussed that VIA's connected to the center of big metal plates above and below the VIA are less susceptible to SIV compared to VIA's connected to line ends either below or on top of the VIA. We support our argumentation and analytical modeling with Finite Element Modeling.