Electrical field dependence of data retention in high-k interpoly dielectrics

Data retention characteristics of aggressively scaled high-k interpoly dielectrics (IPD) with a fully planar stacked cell are thoroughly investigated. Using high temperature retention experiments of devices programmed at threshold voltages comparable to those used for multi-level cell (MLC) operation and reduced equivalent oxide thicknesses (EOT), we show that retention behavior simply depends on the electric field across the IPD, which is in quadratic inverse proportion to the IPD's reduced EOT. In order to overcome the scaling limits guaranteeing the memory cell's reliability, we propose a new high-k stack without the bottom oxide and achieve excellent reliability, less than 0.3 V of charge loss with IPD EOT below 7 nm. Based on a trap-assisted tunneling model, we simulate the charge loss behavior through the high-k IPD and pave the way for further reducing the IPD EOT to realize memory cells with feature sizes beyond sub-30 nm.