Fully programmable decoder architecture for structured and unstructured LDPC codes

In this article we present a fully programmable and scalable partly-parallel LDPC decoder architecture together with an optimum mapping and scheduling algorithm. The proposed algorithm exploits the full parallelism of the architecture at any time for any code, which means that the mapping algorithm achieves 100% utilization of the architecture. The proposed design is fully programmable and can be reconfigured for a different LDPC code by changing the initialization of the control memory. Thus the architecture can be used for a multi-standard decoder which supports decoding of any structured or unstructured LDPC code. Furthermore, the parallelism of the architecture is unconstrained and fully scalable which allows to exchange hardware cost and throughput with fine granularity. In contrast to previously proposed programmable designs our approach uses parallel variable and check node processing and thus doubles the data throughput.