Molecular carbon implant technology for ultra-shallow junction formation and n-MOSFET strain application in a 40nm node logic device

We investigated molecular carbon (C
₁₆
H
₁₀
) implant as a replacement for both a monomer carbon co-implant as well as a Ge pre-amorphization step for ultra-shallow junction (USJ) formation in a p-MOSFET SDE doping process in a 40 nm logic device. Carbon is often used in the p-FET extension sequence because it reduces transient enhanced diffusion (TED) by trapping silicon interstitials. However, a Ge pre-amorphization implant (PAI) is still required because C is too light to self-amorphize under most conditions. The use of molecular carbon opens the possibility of eliminating the Ge PAI, which is known to leave residual end of range damage leading to junction leakage. As device scaling continues previously acceptable implant technologies for p-FET source/drain extensions (SDE) are struggling to meet advanced device requirements. We report device results showing that a single implant of C
₁₆
H
₁₀
can effectively replace a two step Ge + C implant sequence. We also studied the combination of C
₁₆
H
₁₀
, and B
₁₈
H
₂₂
at various energies, beam currents, and doses in terms of R
_s
-X
_j
under different advanced annealing schemes. We have also investigated the possibility of using a different molecular carbon (C
₇
H
₇
) for n-MOSFET drive current enhancement through the formation of a Si:C stressor in the n-MOSFET source/drain (SD) region. Comparisons of XRD and Rs of the molecular carbon implanted samples from different process flow arrangements were made to identify the proper sequence of implants and anneals. Using a blanket wafer test, we demonstrated that molecular carbon implant produces a thick enough amorphous layer for high incorporation of carbon on the silicon lattice. The optimal location and distribution of high carbon concentration regions, which give the highest strain and least impact in SD Rs were determined. C
₇
H
₇
was implanted into the SD region of a 40 nm logic n-MOSFET to verify the results from the blanket wafer test.