A new technique to extract the gate bias dependent s/d series resistance of sub-100nm MOSFETs

In this study, a new technique to extract the S/D series resistance (R
sd
) from the total resistance versus transconductance gain plot R
tot
(1/β) is proposed. The technique only requires the measurement of I
d
(V
gs
)|
Vgt
and β, allowing fast and statistical analysis in an industrial context. Unlike the usual R
tot
(L)-based techniques, it has the advantage of being insensitive to the channel length and mobility variations and finally enables to extract very accurate values for R
sd
(V
gs
) and the effective mobility reduction factor µ
eff
(V
gt
)/µ
eff
(0).