Demonstration of 20 Gbps digital test signal synthesis using SiGe and InP logic

This paper demonstrates the signal performance obtained by combining data from two 10 Gbps SiGe serializers using a very high-speed, low-jitter InP exclusive-OR gate. The technique has been proven for lower-speed (i.e. les12.8Gbps) applications (Keezer et al., 2007). But its success at higher speeds depends upon tight control of timing and signal integrity. Relatively low-cost components are selected so that the method can be applied to test scenarios requiring many high-speed channels. Careful analysis of the demonstration circuit performance reveals the challenges, capabilities, and limitations of the method.