An assigned-buffer ATM switching architecture

There has been a great technological advancement in microelectronics and communications, which forces, among others, investigations on ATM switching architectures. Researchers keep on searching an efficient architecture, able to perform at a wide range of traffic loads and patterns, ensuring both minimum probability of cell loss as well as minimum cell delay. The authors propose one more architecture. The main goal is to create an architecture capable of operating at very high data rates. As the result, the switch uses the fastest method of buffer management, and is characterized by sufficiently low probability of blocking and short delay time. Appropriate simulation results are presented and some implementation issues are discussed.