Accumulation region length impact on 0.18µm CMOS fully-compatible lateral power MOSFETs with Shallow Trench Isolation

N-type lateral power MOSFETs (nLDMOS) with shallow trench isolation (STI) and voltage capability between 12 and 22 V are analyzed in this work by experiment and TCAD simulation. A 0.18 mum CMOS technology is used to integrate nLDMOS devices without additional mask or process. Differently from previous works, the paramount impact of the accumulation region length (Lacc) on the safe operating area (SOA), gate-to-drain charge (Qgd) and hot carrier (HC) degradation is deeply explored to optimize the device electrical performance and reliability.