Three dimensional stacking with diamond sheet heat extraction for subnanosecond machine design

Devices are becoming available whose inherent switching speeds are approaching only a few picoseconds. CMOS FET devices with 0.12 micron channel length have exhibited f/sub T/ values of 89 GHz. SiGe HBTs have been demonstrated with an f/sub T/ of 117 GHz. InP/InGaAs/AlGaAs HBT's have exhibited an f/sub T/ of 200 GHz, with minimum feature sizes that are above one micron. InGaAs/AlGaAs MESFET's with 0.05 micron channel lengths have exhibited f/sub T/ values of 350 GHz. Clearly even faster devices are possible, and some have even begun to appear in viable fabrication lines where prospects for interesting levels of integration are being realized. For such technologies subnanosecond machine cycles seem possible. However, for conventional 2D chip or wafer fabrication some of the distances between key components on these substrates can be too long for subnanosecond operation. This may be true even for ideal transmission line interconnections that exhibit "speed of light" propagation speeds and extremely wide bandwidths. At this point the last resort is to shorten these interconnections by rearranging the components in 3D structures, implying either die or wafer stacking. This paper explores some of the requirements for subnanosecond machine design, and practical schemes to accomplish this with discussion on how to distribute the power supply current and dissipate the heat generated. These schemes use the full array of WSI, WSHP and MCM technologies plus some new techniques for 3D vertical stacking.