Design of inverse DCT unit and motion compensator for MPEG2 HDTV decoding

An MPEG2 video decoder core is implemented, which consists of an inverse discrete cosine transform (IDCT) unit and a motion compensator. By means of butterfly computation, multi-bit extension of distributed arithmetic, and improvement of critical paths, the IDCT unit achieves a high throughput, and the motion compensator calculates half-pel image dynamically so as to cover several types of picture prediction modes employed by MPEG2. The decoder core occupies 27 mm/sup 2/ in a 0.6-/spl mu/m triple-metal CMOS technology, processes a macroblock (16/spl times/16 pels) within 2.5 /spl mu/s, and therefore is capable of decoding HDTV (1920/spl times/1152 pels) resolution images in real time.