A sub-threshold leakage mechanism in multiple-implanted LDD structures in BiCMOS technology

Experimentally verified numerical process and device models have been developed for the LDD PMOS structures of a sub-micron gate BiCMOS process. The models have been used to investigate the sensitivity of the device characteristics to the multiple implant exposures. It is shown that partially uncompensated accepters of such multiple implants can create a depleted buried channel under the gate which behaves like a JFET operating below its pinch-off and conducting in parallel with the MOSFET's surface inversion channel. Such added bulk conduction is shown to conceal itself in lowered subthreshold slope or manifest itself as excess leakage depending on the combination of the implant doses employed in threshold voltage adjustment, LDD, etc.