Design and optimization of a 71 Gb/s injection-locked CDR

High data rate wireline systems suffer from increasing complexity and design difficulty due to stringent system specifications and circuit and technology challenges. A methodology therefore must exist which allows circuit and system challenges to be dealt in an effective manner while paying close attention to the extensive coupling between these two domain. In this work we look at the problem of system and circuit design of a 71 Gb/s Clock and Data Recovery circuit (CDR) in a 180nm SiGe process. To provide power efficient and robust clock recovery (CR) circuits for this system, an injection locked CR block has been implemented, leading to a reduction in circuit components and power consumption over conventional CDRs. The design methodology is based on an iterative approach alternating between circuit and system level design optimization. The core of the circuit consumes 136mW from 3.3V supply. The total circuit consumes 514mW, including 60mW for the limiting amplifiers.