Efficient Array Characterization in the UltraSPARC T2

Arrays constitute increasingly more area in microprocessor designs. Identifying failing cells in these arrays is essential for process characterization and to regain yield by replacing failing cells with redundant cells. Process characterization can be done out of the normal test flow on a sampling of wafers, but identifying failing cells must be done on all wafers to determine if they can be repaired. This paper discloses an economical and novel technique for identifying the state of every cell in an array, and which is currently in use on Sun's UltraSPARC T2 SOC. It can be used under various conditions on a tester to directly observe the array contents, and it is used in the manufacturing test flow to create bit-fail maps at speed. It has also been used in Silicon debug.